The Future of Microprocessors
Recent developments in the microprocessor industry have indicated the end of the uniprocessor design and the emergence of multi-processor architectures. Chip designers have reached the limit of instruction-level parallelism that can be exploited with better pipeline design, as well as the improvements from clock scaling due to packaging and technology constraints. However, the emerging class of multi-processor systems raises a new problem in the interconnection network, the medium that allows all the processors, memory, and IO devices to communicate.
Typical modern day on-chip interconnection networks are implemented as electronic packet switched topologies. In some multi-core architectures, the network accounts for over 50% of the total power consumption of the chip. This proportion will be exacerbated as workload demand on these on-chip networks increases. Also, off-chip bandwidth is limited to the number of metal wires that can be traced off the limited peripheral area, which results in a large mismatch in on- and off-chip bandwidth. In order to alleviate these issues of power and bandwidth, one proposed solution that we and the research community are actively pursuing is the use of a photonic interconnection network.
Bringing photonics to the chip-level can potentially bring increased bandwidth, reduced latency, and improved power efficiency. The main advantage of on-chip nanophotonics lies in the decoupling of distance with power consumption. For chip-scale distances, signals can be modulated once and carried completely to their destination regardless of how far away it is. Conversely, electronics requires buffering every few millimeters, which consumes more power as data travels further. In addition to this key advantage for on-chip communications, photonics brings the added advantage that this concept also applies for chip IO, while maintaining the same bandwidth delivered on-chip! Speed of light in silicon end-to-end propagation can also yield significant improvements in latency. Because optics is not constrained to the common electrical restrictions that prevent high signaling rates across interfaces, it effectively solves the bandwidth mismatch.
Comprehensive Photonic Network Simulator
We are currently developing Photonic and Electronic Network Integration and Execution Simulator (PhoenixSim), a cycle accurate photonic interconnection network simulator suite on top of the OMNeT++ environment. The package is primarily composed of four simulation planes: the photonic plane, the electronic plane, the processing plane, and the IO plane. The photonic plane is a hierarchical structure with very detailed physical models of a number of photonic building blocks which can be used to create more complicated photonic structures, such as a switch or a network. The electronic plane acts as both a way to control the photonic network as well as an independent conventional electronic network, which typically shadows the photonic layout. The processing plane contains the modules that generate traffic, whether it be random, trace-based, or from cycle accurate instruction execution. The IO plane contains DRAM and other storage modeling, as well as bridges to other systems.
This simulation environment is being developed in an extremely dynamic and customizable way to enable it to be used in a variety of ways. The suite can analyze photonic networks at both the physical level, looking at parameters such as insertion loss and crosstalk, as well as at the system level in order to examine network and application performance. This functional diversity is enabled by the variety of other powerful open-source modeling packages we incorporate to increase accuracy. This includes, among others, the cycle accurate micro-architectural simulator SESC, the electronic router power model package ORION, and the DRAM functional and power model DRAMsim.
Photonics for Board-Level Communications
Currently we are investigating ways to bring photonics to both the microprocessor chip and the motherboard. Current computing systems suffer from a bandwidth bottleneck between the processor and memory. Typically processor designs use caching to help hide the latency, but as the number of cores on chip grows, as will the network complexity, careful deliberation of the communication architecture will be extremely important.
Nanophotonic CAD Environment
We are also developing Visual Automated Nanophotonic Design And Layout (VANDAL), a CAD environment for nanophotonic interconnects.
Recent advances in silicon photonic micro-fabrication techniques—the same highly-developed techniques used in the commercial development of the ubiquitous complementary metal–oxide–semiconductor (CMOS) platform—have led to the expansion of a photonic toolbox consisting of key elements which enable the realization of chip-scale photonic interconnection networks in the context of networks-on-chip (NoCs) interconnecting chip multi-processors. Collaborating with leading research groups in this area, we have developed a network-driven design approach for implementing and characterizing these building blocks. Our vision includes a three-dimensional integrated (3DI) monolithically-integrated silicon stack, comprising traditional CMOS and dynamic random access memory (DRAM) technology as well as optoelectronic and other photonic integrated circuit (PIC) devices.
Among the components that we have investigated to support our vision is an electro-optic form-factor translator, which converts space-parallel data from an electronic bus into wavelength-parallel photonic data coinciding on a single waveguide link. We then investigated the ultra-broadband, low-loss photonic link capable of carrying terabits-per-second of information encoded in this wavelength-parallel manner from one node to another.
In our endeavor to investigate practical microring resonator-based dynamic switching functionalities within this silicon platform, we have characterized a multi-wavelength 1×2 switch, capable of switching optical signals with data rates approaching terabits-per-second. Subsequently, we examined a 2×2 switch, which also enables dynamic message routing of wavelength-parallel broadband photonic signals. Combining the demonstrated 1×2 and 2×2 switching functionalities, we then investigated a thermally active 4×4 switch, which enables non-blocking switching functionality within complex network architectures.
In addition to the design and implementation of these components, we have characterized their predominant signal-degrading impairments in an effort to further improve the performance of interconnection networks derived from future versions of these devices. Narrowband filtering of high-speed data signals is an important consideration when passing data through high-quality-factor microring resonators, as is done in the aforementioned multi-wavelength switches. We have experimentally and numerically characterized the power penalty induced by this effect, and applied the numerical simulator to a wide variety of other higher order transfer functions realizable with these devices.