This project focuses on development of high performance computing related models and network simulations, and to expand our in-house simulation engine, PhoenixSim, to support the automation and configuration of SST simulation scripts with graphic user interface.
Computing platforms are increasingly challenged by the need to process growing volumes of data arriving in real time and at very high rates. New memory technologies such as Hybrid Memory Cube (HMC) and High-bandwidth Memory (HBM) provide a Tbps memory access. Optical interconnects based on Silicon Photonic platform enable new distance independent, and reconfigurable compute to memory architectures. Our work spans from the physical layer including transceivers and switches to application demonstration of memory bound applications.
Columbia team works jointly with HPE’s PathForward program in an integrated multidisciplinary effort to leverage photonic, system architecture, and software expertise to develop new photonic enabled Exascale systems designs and drive emerging integrated photonic interconnect technologies. The leading researcher of the PathForward project from LRL is Yanir London.
The Photonic Integrated Networked Energy efficient datacenter (PINE)vision is built on three main innovation pillars: i) redesigning the architecture based on disaggregation of compute and memory resources over a unified photonic interconnect with bandwidth steering capabilities to improve resource allocation throughout the datacenter, ii) introducing a concept of embedded datacenter nodes consisting of various Multi-Chip Modules (MCMs) interconnected in a unique interposer platform via high bandwidth density integrated photonics, and iii) developing a new generat
The Photonic-Storage Subsystem Input/Output (P-SSIO) Interface project aims to provide low-power high I/O bandwidth capacity for the storage subsystem in leadership superclass computers. Energy -efficient Photonic transceiver and Photonic-switched interconnect enable reconfigurable connectivity between hosts and storage devices for the disaggregated system architectures.